Article
Article
- Engineering & Materials
- Physical electronics
- Beyond CMOS technology
DISCLAIMER: This article is being kept online for historical purposes. Though accurate at last review, it is no longer being updated. The page may contain broken links or outdated information.
Beyond CMOS technology
Article By:
Chen, An GLOBALFOUNDRIES, Technology Research Group, Sunnyvale, California.
Last reviewed:2010
DOI:https://doi.org/10.1036/1097-8542.YB100215
- CMOS scaling limits
- Nonclassical CMOS
- Emerging memory and logic devices
- Novel architectures
- Evaluation criteria
- Related Primary Literature
- Additional Reading
In the past several decades, the scaling of silicon metal-oxide-semiconductor field-effect-transistor (MOSFET) technology has been the primary driving force behind the prosperity of the global microelectronics industry. By reducing the size of transistors in an integrated circuit, almost every measure of the integrated circuit's capabilities is improved, such as higher transistor density, lower cost per transistor, and faster transistor speed. Over the past 40 years, transistor feature size has been reduced from 10 micrometers to approximately 30 nanometers. Although most of the time scaling is simply reducing the feature size, during certain periods the industry has made major changes by moving from bipolar transistor to p-channel and n-channel MOS, and finally to complementary MOS (CMOS) planar transistors in the 1980s. Since then CMOS has remained the dominant technology. As the MOSFET size approaches tens of nanometers, this scaling trend is facing an inevitable end, which calls for beyond-CMOS technologies to continue the technological advancement for the microelectronics industry.
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