For over 30 years, predictions that lithography for microelectronics and nanoelectronics would reach its limit have been overcome by engineers pulling out of their hats every imaginable optical trick for shrinking linewidths to cram more and smaller transistors onto the horizontal plane of a single chip. Now, in the quest to build smaller, faster, less-expensive devices, chip architects are following the lead of city planners who ran out of real estate for expanding horizontally: They are looking up. With vertical integration techniques, chipmakers can arrange transistors in three dimensions, not just two. See also: Integrated circuits; Microlithography

Exploiting the third dimension in chip design offers the obvious advantage of helping circuitry stay more compact, which is beneficial in devices such as smartphones, tablets, and portable storage devices (memory sticks). Because vertical integration promises to reduce the average distance between connected components, it can also lower power consumption and boost the data bandwidth or speed (the amount of data communicated per unit time; e.g., GB/s). Building 3D integrated circuits also allows semiconductor fabrication plants (fabs) to increase the density of components on their chips with their existing equipment rather than to replace it with expensive new equipment for shrinking transistors. Considering that a new fab can cost up to $10 billion to build and equip, this is a huge savings.

Currently, there are two approaches for 3D integration: chip scale and chip stacking. In chip-scale integration, layers of circuitry are built directly atop one another, with more layers corresponding to higher density and performance. Such vertical integration has its challenges, however, because lower process temperatures are required to avoid damaging the circuitry. Manufacturers have nonetheless risen to those challenges: in 2013 Samsung produced commercial 3D 128-gigabit flash memory chips with 24 layers, and Micron has announced plans to produce 3D 256-GB flash memory chips. See also: Nonvolatile memory devices; Semiconductor memories

Chip-stacking integration, also known as 3D wafer-level chip packaging, is done by interconnecting a stack of two or more chips with vertical pathways known as through-silicon-vias (TSVs). TSVs are typically less than 30 micrometers (μm) in diameter and use copper as the conducting material. Chips with similar or different functions (for example, a memory chip and a microprocessor) may be stacked. To meet the dimensional requirements of the final package, the thickness of the wafers is reduced from about 750 μm to 50–75 μm by a grinding process called wafer thinning. Handling and dicing of the thinned wafers adds complexity to the process and requires specialized equipment. Two additional challenges in this technology are thermal management (cooling) of the stacked devices during use and the limitation called known good die (meaning that one bad chip will ruin the entire device). Nevertheless, chip stacking can produce devices that have greater density, use half the power, and run twice as fast as individually packaged chips can. See also: Electronic packaging; Microprocessor